In general, a data signal generating apparatus such as PPG (pulse pattern generator) converts, by using a multiplexer, low speed parallel data into high speed serial data, and to output the serial data.
FIG. 11 is a block diagram showing the fundamental construction of the data signal generating apparatus 10 provided with a multiplexer.
As shown in FIG. 11, a data output unit 11 has a memory unit (not shown) having a series of data string stored therein, the data string having a predetermined pattern, or a processing circuit (not shown) for producing a series of data string. The data output unit 11 is operative to output m-bit of data in parallel every time receiving a data request signal A.
A multiplexer 13 has a switch unit 13a for selecting the data, a controller 13b for controlling the change-over operation of the switch unit 13a, and a latch circuit 13c for latching the data inputted in parallel, and outputting the data to the switch unit 13a. The multiplexer 13 is operative to latch m-bits of parallel data outputted from the data output unit 11 and to output the data by one bit as selected serial data in a desired sequence in synchronism with a high speed reference clock signal CK1.
The controller 13b is operative to output a data request signal A produced by dividing the frequency of the reference clock signal CK1 with a number “m” to request a following parallel data every time the data selection by the switch unit 13a is performed (every time the number “m” of the data are outputted). Immediately after the data request signal A is outputted by the controller 13b, the latch signal B is inputted to the latch circuit 13c by the controller 13b. 
Here, it is assumed that for example the number “m” is four. In this case, it is also assumed that in response to the reference clock signal CK1 shown in FIG. 12(a), the data request signal A (rising edge) is outputted to the data output unit 11 at a timing shown in FIG. 12(b). In response to the data request signal A, four bits of parallel data d(0, 0) to d(0, 3) shown in FIGS. 12(c) to 12(f) are produced in a state with entirely no delay times by the data output unit 11 to be inputted to a multiplexer 13.
At a timing elapsed by a somewhat time Δt after the data request signal A is outputted, a latch signal B (rising edge) shown in FIG. 12(g) is outputted to the latch circuit 13c to have the parallel data d(0, 0) to d(0, 3) shown in FIGS. 12(h) to 12(k) given to the switch unit 13a. The switch unit 13a is operable to be changed at each of the falling edge of the reference clock signal CK1 from after the latch signal B is outputted, i.e., at each of the times t00, t01, t02, and t03 to output the data d(0, 0), d(0, 1), d(0, 2), d(0, 3) shown in FIG. 12(i) in this sequence. Afterward, the above operation is repeated to lead to the outputting operation of the serial data in a desired pattern.
The above operational example shown in FIG. 12 has been raised and explained to have no delay times or to be in an ignored delay times between the multiplexer 13 and the data output unit 11, however, there is generally generated a relatively long delay time from the time the data request signal A is received by the data output unit 11 to the time the new parallel data are outputted to the latch circuit 13c due to the fact that the data output unit 11 is in reality constituted partly by a memory. The delay time occurs depending upon the length of each line to transmit the data request signal A and the parallel data Dp. The total of the delay times Td is a level of a few nanos/second (ns) at the smallest.
On the other hand, assuming for example that the frequency f1 of the reference clock signal CK1 is 10 GHz, the previously mentioned delay time Td is a few tenth the frequency T1 (0.1 ns) of the reference clock signal CK1. If the delay time is equal to the m-th (m-multiple) the frequency T1 of the reference clock signal CK1 or the integer k-th (integer k-multiple) the frequency T1 of the reference clock signal CK1, there is generated a state the same as the state shown in FIG. 12 in which the serial data Ds are outputted by the switch unit 13a in the desired sequence as described above.
When, on the other hand, the above delay time becomes equal to mkt+Δt. viz., the data updating timing of the data inputted to the multiplexer 13 from the data output unit 11 is coincident with the reading timing (latch timing), the reading timing of the multiplexer 13 for each of all the bits of the data comes to be unstable so that the desired serial data Ds are not outputted by the multiplexer 13.
On of the known multiplexer is constructed to convert the parallel data into the serial data after the parallel data are latched at one time as described above, and the other of the known multiplexer is constructed to latch the parallel data at a time difference equal to the period of the latching operation of the parallel data in some series sequence in synchronism with the reference clock signal CK1 and then to output as the serial data. In the two known multiplexer, the latching timings of the some series of the parallel data are overlapped with the data updating timings so that there are given rise to some cases in which the output data of the series of the parallel data are unstable and in which the sequence of the output data is brought out of the desired sequence.
As one of known methods to solve these problems, there is a method in which the reference clock signal CK1 is inputted to the multiplexer 13 at a delay time of Td by a delay device 14, and in which the reference clock signal CK1 is divided by 1/m by a frequency divider 15 before the divided reference clock signal CK1 is inputted to the data output unit 11 as a data request signal. The frequency divider 15 thus used in this manner is disclosed for example in the patent document 1 as described below.
As the other alternative known method, there is another proposed method which is disclosed for example in the non-patent document 1 as described below. In the method disclosed in the document 1, in the case that the data output unit 11 is constructed to output a data synchronism clock in synchronism with the updating timing of the parallel data, the phase difference between the divided clock signal CK2 produced by dividing the frequency of the reference clock signal CK1 by the number “m” with a frequency divider 15 and the data synchronism clock CKp outputted from the data output unit 11 is detected to produce a detection signal by a phase comparator 16. The detection signal serves to control VCO17 oscillating and outputting a data request signal A′ having a frequency f/m in the PLL construction as shown in FIG. 15.    Patent document 1: Japanese Patent Laid-Open Publication No. H11-163608    Non-patent document 1: “VSC1237, VSC1238”, [online], Aug. 11, 2004, Vitesse Semiconductor Corporation, [Mar. 23, 2007], Internet